The invention relates to a semiconductor memory device, and more particularly, to an apparatus and method for applying power to a semiconductor memory device.
In general, a semiconductor memory device such as a dynamic random access memory (DRAM) includes a core region for processing data and a data input/output region for exchanging data with another semiconductor device. The data input/output region includes a data input buffer and a data output circuit. The core region also includes a memory array block and a peripheral logic block.
As shown in FIG. 1, the semiconductor memory device such as the DRAM is applied with two types of power VDD/VSS and VDDQ/VSSQ. The VDD power and the VSS power are applied to a memory array block 10 and a peripheral logic block 20, and the VDDQ power and the VSSQ power are applied to a data output driver 30 for outputting data. Except the data output driver 30, all other parts use the VDD power. The VDD power is also used to generate various voltage levels of internal power for effectively performing write and read operations in the DRAM. The VDD power and the VDDQ power are the same level power that is directly applied from the outside of the semiconductor memory device. The VDD power and the VDDQ power are physically separated not only in the outside but also in the inside of the semiconductor memory device.
Meanwhile, a pin-out structure of a DDR3 SDRAM package is divided into a data input/output block and an address block according to the specification of JEDEC standard, as shown in FIG. 2. Herein, DDR3 SDRAM denotes a Double Data Rate 3 Synchronous Dynamic Random Access Memory, and JEDEC denotes Joint Electron Device Engineering Council. The data input/output block includes DQ pins such as DQSU#, DQU6, DQSU, DQU2, and DQL3 for inputting and outputting data. The address block includes address pins A0 to A15, clock pins such as CK and CK#, and command input pins such as CAS#, RAS#, CS#, and WE#. Since the address block includes many VDD power pins and VSS power pins, it is easy to apply the VDD power and the VSS power. On the contrary, it is difficult to additionally dispose VDD power pins and VSS power pins in the data input/output block because the data input/output block VDDQ already includes many VDD and VSS power pins.
Such a pin-out structure of the DDR3 SDRAM package is badly designed to apply power for predetermined operation modes of a semiconductor memory device. For example, the VDD power having a dropped voltage level is applied to a memory array block 10 and a peripheral logic block 20 of a memory bank that is adjacent to a data input/output block as shown in FIGS. 1 and 3 in an operation mode that consumes a large amount of instantaneous current, such as a refresh operation mode, particularly, an auto refresh operation mode. As a result, the operations of the memory array block 10 and the peripheral logic block 20 are performed unstably.